(1) Field of the Invention
The present invention relates to methods for producing integrated circuit devices-having lightly doped drain MOSFET with refractory metal polycide gate structures.
(2) Description of Prior Art
The use of polycide gates or interconnect lines, that is a combination of layers of polysilicon and a refractory metal silicide is becoming very important as the industry moves to smaller device geometries or more compact design. In the past, polysilicon was satisfactory as the gate electrodes and for interconnecting lines. However, as these geometries become smaller, polysilicon has become too high in resistivity for these applications due to its impact on RC time delays and IR voltage drops. The use of a combination of refractory metal silicides with polysilicon has proven suitable because of its lower resistivity.
Silicides of certain refractory metals, i.e. tungsten, molybdenum, titanium, and tantalum have been proven to be suitable for use as a low resistance interconnect material for VLSI integrated circuit fabrication. The disilicides pair very well with heavily doped polysilicon to form polycide gates, because of the criteria of low resistivity and high temperature stability. Tungsten silicide has particularly been found to be capable of overcoming some shortcomings, such as self-passivation, good stability in wet chemical ambients, adhesion, and reproducibility in combination with polysilicon in production.
The preferred deposition technique of tungsten silicide is low pressure chemical vapor deposition. The oxidation characteristics of tungsten silicide as produced by this method are similar to those of polysilicon.
The peeling of the polycide film can happen frequently if care is not taken during processing and handling of the wafers. This in turn causes the low yield of the product. This peeling and/or less integrity of the silicide problems are often observed after thermal treatments especially under an oxidizing atmosphere.
The conventional polycide process forms sequentially the gate oxide layer by thermal oxidation, the polysilicon layer which is then doped, and the refractory metal silicide in situ. The refractory metal silicide and polysilicon layer deposition and the doping of the polysilicon are normally not done in the same reaction chamber. These layers are now anisotropically etched in the desired pattern of polycide gate structures. A furnace annealing step in oxygen causes the amorphous refractory metal silicide to change into its crystalline phase. During this annealing process, silicon dioxide is grown upon the surfaces of the polycide and exposed silicon substrate. A pattern of lightly doped regions in the substrate is formed by ion implantation using said gate electrode structures as the mask. The dielectric spacer is formed by blanket chemical vapor deposition of silicon dioxide, a heat densification step and an anisotropic etching of the silicon dioxide layer. The N+ implant is then carried out, followed by the conventional dopant annealing step. The result of this process is all too often the peeling of the refractory metal silicide.
The workers in the field have tried to overcome this problem by capping with silicon dioxide during the reaction of titanium with the underlying polysilicon layer such as shown by T. E. Tang et al in U.S. Pat. No. 4,690,730. This did suppress peeling for this type of process, however the major reason for the silicon dioxide layer is to prevent the titanium from being oxidized by oxygen.
C. S. Yoo in U.S. Pat. No. 5,089,432 has shown a method for overcoming the metal silicide peeling problem by providing a method with forms a silicon oxide cover layer over the metal silicide layer before the formation of the heavily doped source/drain regions. C. S. Yoo and T. H. Lin in Ser. No. 7/649,549 filed Feb. 1, 1991 have shown a method which uses ion implanted silicon ions into the metal silicide layer to overcome the peeling problems.
It is therefore an important object of this invention to provide a method for fabricating integrated circuits which overcomes this peeling problem and raises yields by using a capping free metal polycide intergrated process which only uses high temperature annealing steps when the metal silicide is covered with a suitable covering that is normally formed in the process sequence.